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? semiconductor components industries, llc, 2001 april, 2001 rev. 2 1 publication order number: mc33560/d mc33560 power management and interface ic for smartcard readers and couplers the mc33560 is an interface ic for smartcard reader/writer applications. it enables the management of any type of smart or memory card through a simple and flexible microcontroller interface. moreover, several couplers can be coupled in parallel, thanks to the chip select input pin (pin #5). the mc33560 is particularly suited to low power and portable applications because of its power saving features and the minimum of external parts required. battery life is extended by the wide operating range and the low quiescent current in stand by mode. a highly sophisticated protection system guarantees timely and controlled shutdown upon error conditions. ? 100% compatible with iso 78163 standard ? wide battery supply voltage range: 1.8 v < v bat < 6.6 v ? programmable v cc supply for 3.0 v or 5.0 v card operation ? power management for very low quiescent current in stand by mode (30 m a max) ? microprocessor wakeup signal generated upon card insertion ? self contained dc/dc converter to generate v cc using a minimum of passive components ? controlled power up/down sequence for high signal integrity on the card i/o and signal lines ? programmable card clock generator ? chip select capability for parallel coupler operation ? high esd protection on card pins (4.0 kv, human body model) ? fault monitoring v batlow , v cclow and i cclim ? all card outputs current limited and short circuit protected ? tested operating temperature range: 25 c to +85 c so24w dw suffix case 751e 1 http://onsemi.com 24 pin connections tssop24 dtb suffix case 948k 1 24 124 23 22 21 20 19 18 17 2 3 4 5 6 7 8 (top view) pgnd pwron int invout ilim crddet rdymod cs reset io crdcon crdc8 c8 c4 l1 vbat 16 15 14 13 9 10 11 12 crdgnd crdvcc asyclkin synclk crdio crdrst crdclk crdc4 device package shipping ordering information device marking information mc33560dtb tssop24 62 units/rail mc33560dtbr2 tssop24 2500 tape & reel mc33560dw so24w 30 units/rail mc33560dwr2 so24w 1000 tape & reel see general marking information in the device marking section on page 23 of this data sheet. power manager and programming clock generator dc/dc converter crddet asyclkin card detector delay level translator l1 ilim pgnd pwron rdymod synclk invout io reset c4 c8 crdcon crdvcc crdio crdrst crdc4 crdc8 crdclk crdgnd vbat vbat int cs figure 1. simplified functional block diagram
mc33560 http://onsemi.com 2 maximum ratings (note 1.) rating symbol value unit battery supply voltage v bat 7.0 v battery supply current i bat 200 ma power supply voltage v cc 6.0 v power supply current i cc 150 ma digital input pins (2, 4, 5, 6, 7, 9, 10, 17, 18, 20, 21) v in i in 0.5 to vbat +0.5 but < 7.0 5.0 v ma digital output pins (3, 4, 8) v out i out 0.5 to vbat +0.5 but < 7.0 10 v ma card interface pins (11, 13, 14, 15, 16, 19) v card i card 0.5 to vcc +0.5 25 v ma coil driver pin (22), ilim (pin 24) power ground (pin 1) i l 200 100 ma esd capability: (note 2.) standard pins (2, 3, 4, 5, 6, 7, 8, 9, 10, 17, 18, 20, 21, 22, 23, 24) card interface pins (11, 13, 14, 15, 16, 19) v esd 2.0 4.0 kv kv so24wb package: power dissipation @ t a = 85 c thermal resistance junction to air p ds r q jas 285 140 mw c/w tssop24 package: power dissipation @ t a = 85 c thermal resistance junction to air p dt r q jat 220 180 mw c/w operating ambient temperature range t a 40 to + 85 c operating junction temperature range t j 40 to + 125 c max. junction temperature (note 3.) t jmax 150 c storage temperature range t stg 65 to + 150 c electrical characteristics these specifications are written in the same style as common for standard integrated circuits. the convention considers current flowing into the pin (sink current) as positive and current flowing out of the pin (source cur rent) as negative. (conditions: v bat = 4.0 v, v cc = 5.0 v nom, pwron = v bat , operating mode, i cc = 10 ma, 25 c t a 85 c, l 1 = 47 m h, r lim = 0 , crdvcc capacitor = 10 m f, unless otherwise noted.) characteristic symbol min typ max unit battery power supply section supply voltage range normal operating range extended operating range (note 4.) v bat 2.2 1.8 6.0 6.6 v mc33560 stand by quiescent current pwron = gnd, crdcon = gnd, asyclkin = gnd, v bat = 6.0 v, all other logic inputs and outputs open i obat 30 s dc operating current i cc = 10 ma ; v cc = 5.0 v, v bat = 6.0 v i batop 12.5 ma v bat undervoltage detection: upper threshold lower threshold hysteresis 1.6 1.4 0.2 v 1. maximum electrical ratings are those values beyond which damage to the device may occur. t a = 25 c. 2. human body model, r = 1500 , c = 100 pf. 3. maximum thermal rating beyond which damage to the device may occur. 4. see figures 2 and 3. this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however preca utions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operat ion, input and output voltages should be constrained to the ranges indicated in the recommended operating conditions.
mc33560 http://onsemi.com 3 v cc = 5.0 v nominal power supply section guaranteed limits characteristic test conditions symbol min typ max unit output voltage 2.2 v v bat 6.0 v 1.0 ma i cc 25 ma 3.0 v v bat 6.0 v 1.0 ma i cc 60 ma v cc 4.75 4.60 5.0 5.0 5.25 5.40 v card v cc undervoltage detection: upper threshold lower threshold switching hysteresis (rdymod output) (see table 4) v t5h v t5l v hys5 4.2 120 4.5 180 v cc 0.14 v mv peak output current v cc = 4.0 v, internally limited (rdymod = l) i cclim 80 ma current limit timeout v cc = 4.0 v t d 160 ms startup current v cc = 2.0 v; 0 c to +85 c 40 c to 0 c i ccst 80 50 ma low side switch saturation voltage i l = 50 ma, pin 22 v sat22 100 160 mv rectifier on saturation voltage i l = 50 ma, pin 22 to pin 13 v fsat22 400 520 mv converter switching frequency t a = 25 c f sw 120 khz shut down current (card access deactivated) pwron = gnd, v cc = 2.0 v i sd 80 ma v cc = 3.0 v nominal power supply section (v bat = 2.5 v, i cc = 5.0 ma) guaranteed limits characteristic test conditions symbol min typ max unit output voltage 2.2 v v bat 6.0 v 1.0 ma i cc 10 ma 2.5 v v bat 6.0 v 1.0 ma i cc 50 ma v cc 2.75 2.60 3.0 3.0 3.25 3.40 v card v cc undervoltage detection: upper threshold lower threshold switching hysteresis (rdymod output) (see table 4) v t3h v t3l v hys3 2.4 80 2.7 110 v cc 0.1 v mv startup current shut down current (card access deactivated) v cc = 2.0 v pwron = gnd, v cc = 2.0 v i ccst i sd 50 50 ma application interface dc section (v bat = 5.0 v) guaranteed limits characteristic test conditions symbol min typ max unit input high threshold voltage (increasing) pins 2, 4, 5, 6, 10, 17 v ih 0.55*v bat 0.65*v bat v input low threshold voltage (decreasing) pins 2, 5, 6, 10 pin 17 pin 4 v il 0.3*v bat 0.2*v bat 0.3*v bat 0.45*v bat 0.40*v bat 0.5*v bat v switching hysteresis pins 2, 4, 5, 6, 10, 17 v hyst 0.06*v bat 0.3*v bat v threshold voltage pin 9 pin18 v th 0.5*v bat 0.4*v bat 0.6*v bat 0.6*v bat v pulldown resistance v in = v bat 1.0 v, pin 2, 6, 7, 10 r down 120 240 500 k pullup resistance v in = 0.5 v, pin 3, 4, 5 r up 120 240 500 k output high voltage i oh = 2.5 m a, pin 3, pin 4 for cs = h i oh = 50 m a, pins 7, 20,21 i oh = 0.2 ma, pin 8 pin 4 ( in output mode) v oh v bat 1 v output low voltage i ol = 1.0 ma, pins 7, 20, 21 i ol = 0.2 ma, pins 3, 4, 8 v ol 0.4 v input leakage current v in = 2.5 v, cs = h, pins 9, 17, 18, 20, 21 +/ileak 2.0 a
mc33560 http://onsemi.com 4 card interface dc section (v bat = 5.0 v) guaranteed limits characteristic test conditions symbol min typ max unit output high voltage i oh = 20 m a, pin 11, 16, 19 i ol = 0.2 ma, pins 14, 15 v oh v cc 0.9 v output low voltage i ol = 1.0 ma, pins 11, 16, 19 i ol = 0.2 ma, pins 14, 15 v ol 0.4 v i/o pullup resistance, operating mode, cs =l, pwron =h v ol = 0.5 v, pin 11, 16, 19 18 k card pins security voltage (card access deactivated) pwron = gnd, lin=10 ma, pin 11, 14, 15, 16, 19 v security 2.0 v digital dynamic section (v bat = 5.0 v, normal operating mode) (note 6.) guaranteed limits characteristic test conditions symbol min typ max unit input clock frequency pin 9, duty cycle = 50% f asyclk 20 mhz card clock frequency pin 15 f crdclk 20 mhz card clock duty cycle (note 7.) pin 15, 50% to 50% v cc , f io = 16 mhz r clk 45 55 % card clock rise and fall time pin15, 10% ? 90% v cc t rclk , t fclk 10 ns i/o data transfer frequency pin [7, 11], [21, 16], [20, 19] (note 8.) f io 1.0 mhz i/o duty cycle pin [7, 11], [21, 16], [20, 19] (note 8.) 50% to 50% v cc r io 45 55 % i/o rise and fall time pin [7, 11], [21, 16], [20, 19] (note 8.) 10% ? 90% v cc t rio , t fio 150 ns i/o transfer time pin [7, 11], [21, 16], [20, 19] (note 8.) 50% to 50% v cc , l h, h l t tr 100 ns card signal sequence interval pin 11, 14, 15, 16, 19, v cc power up/down t dseq 0.2 1.0 s card detection filter time: card insertion card extraction t fltin t fltout 50 50 150 150 s s internal reset delay res , v cc power up/down t dres 20 s ready delay time pin 4 t drdy 2.0 s pwron low pulse width cs = l, pin 2 t won 2.0 s digital dynamic section (v bat = 5.0 v, programming mode) (note 6.) guaranteed limits characteristic test conditions symbol min typ max unit data setup time rdymod, pwron, reset, io pin 2, 4, 6, 7 t smod 1.0 s data hold time rdymod, pwron, reset, io pin 2, 4, 6, 7 t hmod 1.0 s cs low pulse width pin 5 t wcs 2.0 s 5. the transistors t1 on lines io, c4 and c8 (see figure 24) have a max rdson of 250 . 6. pin loading = 30 pf, except invout = 15 pf. 7. as the clock buffer is optimized for low power consumption and hence not symmetrical, clock signal duty cycle is guaranteed f or divide by 2 and divide by 4 ratio. 8. in either direction.
mc33560 http://onsemi.com 5 0 200 ibatop (ma) frequency (mhz) figure 2. maximum battery and card supply current vs. v bat (v cc = 5.0 v) vbat (v) figure 3. maximum battery and card supply current vs. v bat (v cc = 3.0 v) figure 4. battery current vs. input clock frequency (i cc = 0, v bat = 4.0 v) figure 5. battery current vs. input clock frequency (i cc = 0, v bat = 2.5 v) figure 6. maximum battery current vs. r lim (v cc = 5.0 v, v bat = 4.0 v) figure 7. maximum battery current vs. r lim (v cc = 3.0 v, v bat = 2.5 v) 40 20 0 6 4 2 0 2.5 3.5 7.5 2.0 4.0 6.0 8.0 10 icc max 4.5 5.5 6.5 180 i (ma) 8 async async/2 sync ibatop max 60 80 100 120 140 160 1.5 mode sync synclk=4mhz l1=47 m h rlim=0 200 vbat (v) 40 20 0 2.5 3.5 7.5 icc max 4.5 5.5 6.5 180 i (ma) ibatop max 60 80 100 120 140 160 1.5 mode sync synclk=4mhz l1=47 m h rlim=0 async/4 vbat=4v l1=47 m h rlim=0 icc=0 12 14 16 10 12 14 0 ibatop (ma) frequency (mhz) 6 4 2 0 2.0 4.0 6.0 8.0 10 8 async async/2 sync async/4 vbat=2.5v l1=47 m h rlim=0 icc=0 12 14 16 10 12 14 250 rlim (ohms) 50 0 12 l1=47 m h 34 ibatop max (ma) l1=100 m h 100 150 200 0 mode sync synclk=4mhz vbat=4v 5 l1=22 m h 250 rlim (ohms) 50 0 12 l1=47 m h 34 ibatop max (ma) l1=100 m h 100 150 200 0 mode sync synclk=4mhz vbat=2.5v 5 l1=22 m h
mc33560 http://onsemi.com 6 figure 8. maximum card supply current vs. r lim (v cc = 5.0 v, v bat = 4.0 v) figure 9. maximum card supply current vs. r lim (v cc = 3.0 v, v bat = 2.5 v) figure 10. low side switch saturation voltage (i l = 50 ma) vs. temperature figure 11. rectifier on saturation voltage (i l = 50 ma) vs. temperature figure 12. card detection (insertion) filter time vs. temperature figure 13. card detection (extraction) filter time vs. temperature 100 rlim (ohms) 20 0 12 l1=47 m h 34 icc max (ma) l1=100 m h 40 60 80 0 mode sync synclk=4mhz vbat=4v 5 l1=22 m h 100 rlim (ohms) 20 0 12 l1=47 m h 34 l1=100 m h 40 60 80 0 mode sync synclk=4mhz vbat=2.5v 5 l1=22 m h icc max (ma) 120 120 t a , ambient temperature ( c) 0.02 0.01 0.00 -5 15 95 35 55 75 low side switch saturation voltage (v) 0.03 0.04 0.05 0.06 0.07 0.08 -25 t a , ambient temperature ( c) 0.10 0.05 0.00 -5 15 95 35 55 75 rectifier on saturation voltage (v) 0.15 0.20 0.25 0.30 0.35 -25 t a , ambient temperature ( c) t a , ambient temperature ( c) 80 75 70 115 tfltin, filter time ( s) 85 90 95 100 105 110 80 75 70 115 tfltout, filter time ( s) 85 90 95 100 105 110 -5 15 95 35 55 75 -25 -5 15 95 35 55 75 -25 m m
mc33560 http://onsemi.com 7 -25 350 pull down resistance (k ) figure 14. pull down resistance vs. temperature t a , ambient temperature ( c) figure 15. transition from 5.0 v to 3.0 v card supply figure 16. transition from 3.0 v to 5.0 v card supply figure 17. overcurrent shutoff (t d = 160 ms) 290 210 150 -5 15 75 35 55 310 230 170 330 250 190 270 95 figure 18. undervoltage shutoff (v t5l = 4.6 v)
mc33560 http://onsemi.com 8 240 k 240 k 240 k 240 k vbat vbat vbat vbatok vbat crdvcc seq1 cardenable vbatok bidirectional i/o vbat crdvcc seq3 cardenable vbatok bidirectional i/o vbat crdvcc seq3 cardenable vbatok bidirectional i/o vbat crdvcc seq4 cardenable vbat crdvcc crdc4 crdc8 crdrst crdclk crdvcc crdvcc crdio l1 ilim crddet crdcon program cardenable card pins sequencer seq1 seq2 seq3 seq4 240 k 240 k 240 k fault on/off 3v/5v dc/dc converter vbat pwron cs rdymod int io c4 c8 reset synclk asyclkin invout seq2 program clock generator and programming data latch level shift level shift crdvcc card power management logic and programming fault logic cs cs pwron s r q vbat vbat vbatok delay 50 s figure 19. functional block diagram
mc33560 http://onsemi.com 9 table 1. pin function description pin symbol type name/function controller interface 2 pwron input pull down this pin is used to start operation of the internal dc/dc converter. in programming mode, this pin is used to set the aoutput voltageo switch. (see table 2). 3 int output pull up this open collector pin indicates a change in the card presence circuit status. when a card is inserted or extracted, the pin goes to logic level a0o. the signal is reset to logic level a1o upon the rising edge of cs or upon the rising edge of pwron. in the case of a multislot application, two or more int outputs are connected together and the microcontroller has to poll all the mc33560s to identify which slot was detected. 4 rdymod i/o & pull up this bidirectional pin has tristate output and schmitt trigger input. * when rdymod is forced to 0, the mc33560 can be set to programming mode by a negative transition on cs . * when rdymod is connected to a high impedance, the mc33560 is in normal operating mode, and rdymod is in output mode (see tables 2 and 4): with cs =l and pwron=h, rdymod indicates the status of the dc/dc converter. with cs =l and pwron=l, rdymod indicates the status of the card detector. 5 cs input pull up this is the mc33560 chip select signal. pins 2, 6, 7, 10, 20, 21 are disabled when cs =h. when rdymod=l, the mc33560 enters programming mode upon the falling edge of cs . (see figure 20) 6 reset input pull down the signal present at this input pin is translated to pin 14 (the card reset signal) when cs =l. the signal on this pin is latched when cs =h. this pin is also used in programming mode. (see table 2) 7 io i/o this pin connects to the serial i/o port of a microcontroller. a bidirectional level translator adapts the serial i/o signal between the smartcard and the microcontroller. the level translator is enabled when cs =l. the signal on thispin is latched when cs =h. this pin is also used in programming mode. (see table 2) 8 invout clk output the asyclkin (pin 9) signal is buffered and inverted to generate the output signal invout. this output is used for multislot applications, where the asyclkin inputs and invout outputs are daisychained. (see the multislot application example in figure 31) 9 asyclkin clk input high impedance this pin can be connected to the microcontroller master clock or any clock signal for asynchronous cards. the signal is fed to the internal clock selector circuit, and is translated to crdclk at the same frequency, or divided by 2 or 4, depending on programming. (see table 3) 10 synclk clk input pull down this function is used for communication with synchronous cards, and the pin is generally connected to the controller serial interface clock signal. the signal is fed to the internal clock selector circuit, and is translated to crdclk upon appropriate programming of the mc33560 (see table 3). when selected at programming, the signal on this pin is latched when cs =h. 20 c8 i/o general purpose input/output. it has the same behavior as i/o, except for programming. it can be connected to a bidirectional port of the microcontroller. the level translator is enabled when cs=l, and the signal is latched whencs=h. (compare with pin 19) 21 c4 i/o general purpose input/output. it has the same behaviour as i/o, except for programming. it can be connected to a bidirectional port of the microcontroller. the level translator is enabled when cs =l, and the signal is latched when cs =h. (compare with pin 16) card interface 11 crdio i/o this pin connects to the serial i/o pin of the card connector. a bidirectional level translator adapts the serial i/o signal between the card and the microcontroller. (compare with pin 7) 14 crdrst output this pin connects to the reset pin of the card connector. a level translator adapts the reset signal driven by the microcontroller. (compare with pin 6) 15 crdclk output this pin connects to the clk pin of the card connector. the crdclk signal is the output of the clock selector circuit.the clock selection is programmed using pins 2, 6 and 7 with rdymod forced to a0o. 16 crdc4 i/o general purpose input/output. it has the same behavior as crdio. it can be connected to the c4 pin of the card connector. 17 crddet input high impedance this pin connects to the card detection switch of the card connector. card detection phase is determined with pin 18. this pin needs an external pullup or pulldown resistor to operate properly.
mc33560 http://onsemi.com 10 pin name/function type symbol card interface 18 crdcon input high impedance this pin connects to pgnd or vbat, or possibly to an output port of the microcontroller. with this pin set to a logic a0o, the presence of a card is signalled with a logic a1o on pin 17. with this pin set to a logic a1o, the presence of a card is signalled with a logic a0o on pin 17. 19 crdc8 i/o general purpose input/output. it has the same behavior as crdio. it can be connected to the c8 pin of the card connector. current limit and thermal protection 1 pgnd power this pin is the return path for the current flowing into pin 22 (l1). it must be connected to crdgnd using appropriate grounding techniques. 12 crdgnd power this pin is the signal ground. it must be connected to the ground pin of the card connector. it is the reference level for all analog and digital signals. 13 crdvcc power this pin connects to the v cc pin of the card connector. it is the reference level for a logic a1o of pins 11, 14, 15, 16 and 19. 22 l1 power this pin connects to an external inductance for the dc/dc converter. please refer to the description of the dc/dc converter functional block. 23 vbat power this pin is connected to the supply voltage. logic level a1o of pins 2 to 10, 17, 18, 20 and 21 is referenced to v bat . operation of the mc33560 is inhibited when v bat is lower than the minimum value. 24 ilim power this pin can be connected to the pgnd pin, or to a resistor connected to pgnd, or left open, depending on the peak coil current needed to supply the card. programming and status functions the mc33560 features a programming interface and a status interface. figure 20 shows how to enter and exit programming mode; table 2 shows which pins are used to access the various functions. pwron cs rdymod (in) io reset program data value program data value program data value enter programming mode latch program value exit programming mode figure 20. mc33560 programming sequence table 2. pin use for programming and status functions programs crdvcc to 3v/5v select vcc on/off select clock input program asyclkin divide ratio poll card status poll crdvcc status rdymod (in/out) force to 0 read force to 0 force to 0 read read cs (in) rising edge 0 rising edge rising edge 0 0 pwron 0/1 0/1 programs crdvcc programs crdvcc 0 or hiz 1 reset (in) programs clk input/divide ratio not used 0/1 0/1 not used not used io (in) programs clk input/divide ratio not used 0/1 0/1 not used not used
mc33560 http://onsemi.com 11 card vcc and card clock programming the crdv cc and asyclk programming options allow the system clock frequency to be matched to the card clock frequency and to select 3.0 v or 5.0 v crdv cc supply. t able 3 shows the values of pwron , reset and io for the possible options. the default power reset condition is state 4 (synchronous clock and crdv cc =5.0 v). all states are latched for each output variable in programming mode at the positive transition of cs (see figure 20). table 3. card vcc and card clock truth table state# pwron reset io crdv cc crdclk 0 l l l 3v synclk 1 l l h 3v asyclkin/4 2 l h h 3v asyclkin/2 3 l h l 3v asyclkin 4 h l l 5v synclk 5 h l h 5v asyclkin/4 6 h h h 5v asyclkin/2 7 h h l 5v asyclkin note : card clock integrity is maintained during all frequency commutations (no spikes). state 4 is the default state at power on. dc/dc converter and card detector status the mc33560 status can be polled when cs = l . please consult table 2 for a description of input and output signals.the significance of the status message is described in table 4. table 4. rdymod status messages pwron (input) rdymod (output) message low low no card low high card present high low dc/dc converter overload high high dc/dc converter ok
mc33560 http://onsemi.com 12 detailed operating description introduction the mc33560 smartcard interface ic has been designed to provide all necessary functions for safe data transfers between a microcontroller and a smartcard or memory card. a card detector scans for the presence of a card and generates a debounced wakeup signal to the microcontroller. communication and control signal levels are translated between the digital interface and the card interface by the voltage level translator, and the card clock is matched to the system clock frequency by the programmable card clock generator. the power management unit enables the dc/dc converter for card power supply, supervises the power up/down sequence of the card's i/o and signal lines, and keeps the power consumption very low in stand by mode. all card interface pins have adequate esd protection, and fault monitoring (v batlow , v cclow , i cclim ) guarantees hazardfree card reader operation. several mc33560s can be operated in parallel, using the same control and data bus, through the use of the chip select signal c s. figure 21. mc33560 operating modes stand by mode cs = h pwron = l cs: rising edge active mode cs = l pwron = l cs: falling edge iso stop sequence idle mode cs = h pwron = h error condition programming mode cs = l rdymod = l cs: 0 and pwron: rising edge iso start sequence transaction mode cs = l pwron = h pwron: falling edge or error condition programming mode cs = l rdymod = l cs: falling edge rdymod: 0 and cs: 1 and rdymod: rising edge cs: 1 and rdymod: rising edge cs: falling edge rdymod: 0 and operating modes the mc33560 has five operating modes: ? stand by ? programming ? active ? transaction ? idle the transitions between these different states are shown in figure 21 above. stand by mode stand by mode allows the mc33560 to detect card insertion and monitor the power supply while keeping the power consumption at a minimum. it is obtained with cs =h and pwron=l . when the mc33560 detects a card, int is asserted low to wake up the microcontroller. programming mode the programming mode allows the user to configure the card v cc and the card clock signal for his specific application. the card supply, crdv cc , can be programmed to 3v or 5v, and the card clock signal can be defined to be either synchronous, or asynchronous divided by 1, 2 or 4. programming mode is obtained with rdymod=l followed by a negative transition on cs . the programming options are shown in table 3. programmed values are latched on a positive transition of cs with rdymod=l . active mode in active mode, the mc33560 is selected, the rdymod pin becomes an output, and the mc33560 status can be polled. power is not applied to the card. the microcontroller polls the mc33560 by asserting cs =l and reading the rdymod pin. if a card is present, the microcontroller starts the dc/dc converter by asserting pwron=h . this starts the automatic power on sequence: when crdv cc reaches the undervoltage level (v t5h or v t3h , depending on programming), the card sequencer validates crdio , crdrst , crdclk , crdc4 , crdc8 pins according to the iso78163 sequence (see figure 26). the mc33560 is now in transaction mode, and the system is ready for data exchange via the three i/o lines and the reset line. transaction mode in transaction mode, the mc33560 maintains power and the selected clock signal applied to the card, and the levels of the io , reset , c4 and c8 signals between the microcontroller and the card are translated depending on the supply voltages v bat and v cc . the dc/dc converter status can be monitored on the rdymod pin. idle mode idle mode is used when maintaining a card powered up without communicating with it. when an asynchronous clock is used, the selected clock signal is applied to the card. power down operation powerdown can be initiated by the controlling microprocessor, by stopping the dc/dc converter with pwron=l while cs =l , or by the mc33560 itself when an error condition has been detected (crdv cc undervoltage, overcurrent longer than 160 ms typ., overtemperature, ahoto
mc33560 http://onsemi.com 13 card extraction). the communication session is terminated in a given sequence defined in iso78163. the mc33560 then goes into active mode, in which its status can be polled. stand by mode is reached by deselecting the mc33560 ( cs = h ). functional blocks card detector this block monitors the card contact crddet (during insertion and extraction), filters the incoming waveform and generates an interrupt signal int after each change. in order to identify which coupler activated the int line (multicoupler application) the microcontroller scans both circuits via cs and reads the rdymod pin. the programming input crdcon tells the level detector which type of mechanical contact is implemented (normally open or normally closed). special care is taken to hold the current consumption very low on this part of the circuit which is continuously powered by the vbat supply. the crddet pin has high impedance input, and an external resistor must be connected to pullup or pull down, depending on crdcon . this resistor is chosen according to the maximum leakage current of the card connector and the pcb. the card detector has an internal 50 m s debouncing delay. the micro controller has to insert an additional delay (in the ms range) to allow the card contacts to stabilize in the card connector before setting pwron = h . when the card detector circuit detects a card extraction, it activates the powerdown sequence and stops the converter, regardless of the pwron signal. the 50 m s delay of the debouncer is enough to ensure that all card signals have reached a safe value before communication with the card takes place. card status the controlling microprocessor is informed of the mc33560 status by interrupt and by polling. when a card is extracted or inserted, the int line is asserted low. the interrupt is cleared upon the rising edge of cs or upon the rising edge of pwron ( int line set to high state). the microprocessor can poll the status at any time by reading the rdymod pin with proper pwron setting (see tables 2 and 4). since int and rdymod have a high value pullup resistor (240 k typ.), their rise time can be as long as 10 m s if parasitic capacitance is high and no other pullup circuitry is connected. power manager the task of the power manager is to activate only those circuit functions which are needed for a determined operating mode in order to minimize power consumption (see figure 19). in stand by mode ( pwron = l ) the power manager keeps only the acard presento detector alive. all card interface pins are forced to ground potential. in the event of a powerup request from the microcontroller ( pwron l to h transition, cs = l ) the power manager starts the dc/dc converter. as soon as the crdvcc supply reaches the operating voltage range, the circuit activates the card signals in the following sequence: crdvcc, crdio, crdclk, crdc4/c8, crdrst at the end of the transaction ( pwron reset to l , cs =l ) or forced card extraction, the crdvcc supply powers down and the card signal deactivation sequence takes place: crdrst, crdc4/c8, crdclk, crdio, crdvcc when cs = l , the bidirectional signal lines ( i o , c4 and c8 ) are put into high impedance state to avoid signal collision with the microcontroller in transmission mode. battery undervoltage detector the task of this block is to monitor the supply voltage, and to allow operation of the dc/dc converter only with valid voltage (typically 1.5 v). the comparator has been designed to have stability better than 20mv in the temperature range. dc/dc converter upon request from the power manager, the dc/dc converter generates the crdvcc supply for the smartcard. the output voltage is programmable for 3.0 v or 5.0 v (see table 3) to guarantee full cross compatibility of the reader for 5.0 v and 3.0 v smartcards. the wide voltage supply range, 1.8 v < v bat < 6.6 v, accommodates a broad range of coupler applications with different battery configurations (single cell or multiple cells, serial or parallel connections). the crdvcc is currentlimited and shortcircuitproof. to avoid excessive battery loading during a card shortcircuit, a current integration function forces the powerdown sequence (see figure 28). to retry the session, the microprocessor works through the power on sequence as defined in the power manager section. dc/dc converter operating principles the dc/dc converter architecture used in the mc33560 allows stepup and stepdown voltage conversion to be done. the unique regulation architecture permits an automatic transition from stepup to stepdown, and from zero to full load, without affecting the output characteristics. dc/dc converter description: the converter architecture is very similar to the boost architecture, with an active rectifier in place of the diode. the switching transistor is connected to ground through a resistor network in order to adjust the maximum peak current (see figure 22). a transistor connected to the converter output ( crdvcc ) forces this pin to a low voltage when the converter is not operating. this prevents erratic voltage supply to the smartcard when not in use.
mc33560 http://onsemi.com 14 the mc33560 has a built in oscillator; the dc/dc converter requires only one inductor and the output filtering capacitor to operate. stepup operation: when the card supply voltage is lower than the battery voltage, the converter operates like a boost converter; the active rectifier behavior is similar to that of a diode. stepdown operation: when the card supply voltage is higher than the battery voltage, the rectifier control circuit puts the power rectifying transistor in conduction when the l 1 voltage reaches v bat +v fsat22 . the voltage across the rectifying transistor is higher than in stepup operation. the efficiency is lower, and similar to a linear regulator. fault detection: the dc/dc converter has several features that help to avoid electrical overstress of the mc33560 and of the smartcard, and help to ensure that data transmission with the smartcard occurs only when its supply voltage is within predetermined limits. these functions are: ? overtemperature detection, ? current limitation, and ? card supply undervoltage detection. the level at which current will be limited is defined by the maximum card supply current programmed with the external components l1 and rlim. the undervoltage detection levels for 3.0 v and 5.0 v card supply are preset internally to the mc33560. figure 22. dc/dc converter functional block pwn low side feed vbat on /off l1 back clock off stop on /off + - - + logic and counter over temp detection digital filter - + on /off rectifier control switch 120 mv pgnd ilim rlim (external) internal resistors 2 0.5 on /off rectifier switch crdvcc active pull-down switch 3v/5v crdgnd vref under voltage detector error amp. vbatok converter fault crdgnd ilimcomp the overcurrent and undervoltage protection features are complementary, and will shut the circuit off either if the overcurrent is high enough to bring the crdvcc output below the preset threshold, either after 160 ms (typ.) in addition, the dc/dc converter will be allowed to start only if the battery supply voltage is high enough to allow normal operation (1.8 v). the undervoltage comparator has a hysteresis and a delay of typically 20 ms to ensure stable operation. the current detector is a comparator associated with two resistors: one 2.0 attached to pgnd and usually connected to analog ground, and a 0.5 attached to ilim , usually connected to ground through an external resistor to adjust the maximum peak current. the voltage developed across this resistor network is then compared to a 120 mv (typical) reference voltage, and the comparator output performs a cyclebycycle peak current limitation by switching off the low side transistor when the voltage exceeds 120 mv. the internal ilimcomp signal is monitored to stop the converter if current limitation is continuously detected during 160 ms (typical). this allows normal operation with high filtering capacitance and low peak current, even at converter startup. as a result, a short circuit to ground on the card connector or a continuous overcurrent is reported by rdymod 160 ms (typical) after power up. unexpected card extraction : the mc33560 detects card extraction and runs a power down sequence if card power is still on when extraction occurs. an active pulldown switch clamps crdvcc to gnd within 150 m s (max) after extraction is detected. the external capacitors will then be discharged. w ith typical capacitor values of 10 m f and 47 nf as indicated in the application schematic, the time needed to discharge crdvcc to a voltage below 0.4 v can be estimated to less than 750 m s. the total time aftercard extraction detection until crdvcc reaches 0.4 v is then estimated to 900 m s (max). all smartcard connector contacts will be deactivated before crdvcc deactivation. this ensures that no electrical damage will be caused to the smartcard under abnormal extraction conditions.
mc33560 http://onsemi.com 15 3.0 v/5.0 v programming: it is possible to set the card supply voltage to 3.0 v or 5.0 v at any time, before dc/dc converter start, or during converter operation. when switching from 3.0 v to 5.0 v, a 160 ms (typical) delay blanks the undervoltage fault detection to allow filter capacitor charging. pwm: the freerunning integrated oscillator has two working modes: ? variable onstate and fixed frequency (typically 120 khz) for average to heavy loads. ? variable onstate and variable frequency for light loads. the frequency can be as low as a few khz if no load is connected to crdvcc . the charging current of the timing capacitor is related to the v bat supply voltage, to allow better line regulation, and to increase stability. filtering capacitor: a high value allows efficient filtering of card current spikes. low values allow low startup charging current. care must be taken not to combine low capacitor value with high current limiting, as this can generate high ripple. usual values range from 4.7 m f to 47 m f, depending on current limiting. selecting the external components l1 and rlim: the choice of inductor l1 and resistor r4 is made by using figure 8 (5.0 v card) and/or figure 9 (3.0 v card) on page 8: first, determine the maximum current that the application requires to supply to the card (iccmax, on the yaxis) then, select one curve that crosses the selected iccmax level. the curve is associated with an inductance value (22 m h, 47 m h, or 100 m h). finally, use the intersection of the curve and the iccmax level to find the rlim value on the xaxis. good starting values are : l1 = 47 m h; r lim = 0.5 note also that, for a high inductance value (100 m h), the filtering capacitor is generally charged before inductance current reaches current limitation, while for alow inductance value, the current limitation is activated after a few converter cycles. battery requirements: having determined the l 1 and r lim values, the maximum current drawn from the battery supply is shown by the curves in figures 6 and 7. when the application is powered by a single 3.0 v battery, special care has to be taken to extend its lifetime. when lithium batteries approach the endoflife, their internal resistance increases, while voltage decreases. this phenomenon can prevent the startup of the dc/dc converter if the current limiting is set too high, because of the filtering capacitor charging current. clock generator the primary purpose of the clock generator module is to match the smartcard operating frequency to the system frequency. the source frequency can be provided to asyclkin by the microcontroller itself or from an external oscillator circuit. in programming mode ( rdymod=l and cs asserted low) the three input variables pwron , io and reset are used to configure the two output variables crdvcc and crdclk as described in table 3. this circuit setup is latched during the positive transition of cs . furthermore, in asynchronous mode the system clock frequency asyclkin can be divided by a factor of 1, 2 or 4. the circuit controls the frequency commutation to guarantee that the card clock signal remains free from spikes and glitches. in addition, this circuit ensures that crdclk signal pulses will not be shorter than the shortest and/or longer than the longest of the clock signals present before and after programming changes. the invout output is provided to drive other circuits without additional load to the microprocessor quartz oscillator. it can also be used to build a local rc oscillator. this driver has been optimized for low consumption; it has no hysteresis, and input levels are not symmetrical. if the asyclkin pin is connected to a sine wave, the duty cycle will not always be 50% at invout . clock generator operating principles synchronous clock: this clock is used mainly for memory cards. it can also be used for asynchronous (microprocessor) cards, allowing the use of two different clock sources. the status of synclk is latched at crdclk when cs goes high, so that data (the io pin) and clock are always consistent at the card connector, whatever the cs status is. when using the synchronous clock, the clock output becomes active only when the mc33560 is selected with cs . asynchronous clock: this clock is used mainly for microprocessor cards. when applied, the clock output remains active even when the mc33560 is not selected with cs , in order to keep the microprocessor running and avoid an unwanted reset. the asyclkin signal is buf fered at the invout pin, so that several mc33560 systems can use the same clock with one load only. depending on programming, the frequency is fed directly, or divided by 2 or by 4 to the crdclk pin. if the duty cycle of the applied clock signal is not exactly symmetrical, it is recommended that the clock signal be divided by two or four to guarantee 50% duty cycle. clock signal synchronization and consistency (see figure 29). the clock divider includes synchronization logic that controls the switch from synchronous clock to asynchronous (and viceversa), from any division ratio to any other ratio, during cs changes and at power up. the synchronization logic guarantees that each clock cycle on the crdclk pin is finished before changing clock selection (and has always the adequate duration), regardless of the moment the programming is changed. at powerup, when asyclkin is selected, the clock signal at the crdclk pin has an entire length, according to the selected divide ratio, whatever the asyclkin signal is versus the internal sequencer timing.
mc33560 http://onsemi.com 16 figure 23. clock generator functional block io reset synclk asyclkin invout cardenable synchronisation logic selector selector latch synchro latch crdvcc crdclk seq3 program 2 latch 2 bidirectional level translator this module (used on io/crdio , c4/crdc4 , c8/crdc8 , see figure 24) adapts the signal voltage levels of the i/o and control lines between the micro controller (supplied by v bat ) and the smartcard (supplied by crdv cc ) when cs is low, with crdvcc on, and start sequencing completed, this module is transparent for the data, and acts as if the card was directly connected to the reader microcontroller. the core of the level shifter circuit defined for the bidirectional crdio , crdc4 and crdc8 lines consists of a nmos switch which can be driven to the logic low state from either side (microcontroller or card). if both sides work in transmission mode with opposite phase, then signal collision on the line is not avoidable. in this case, the peak current is limited to a safe value for the integrated circuit and the smartcard. during hightolow transitions, the nmos transistor impedance (t1 = 250 max.) is low enough to charge parasitic capacitance, and have a high enough dv/dt. on low to high transition, the nmos transistor is not active above a certain voltage, and an acceleration circuit is activated to ensure a high dv/dt. when the chip is disabled ( cs = h ) with the voltage supply crdvcc still active, the io , c4 and c8 lines keep their last logic state. when the converter is off, a transistor forces the crdio , crdc4 and crdc8 lines to a low state, thus preventing any unwanted voltage level to be applied to the data lines when the card is not in use. figure 24. bidirectional translator functional block io vbat 18 k control logic seq1 (seq3) t2 crdio crdgnd cardenable (c4) (c8) t1 (crdc4) (crdc8) crdvcc security features the mc33560 has a number of unique security functions to guarantee that no electrical damage will be caused to the smartcard: ? battery supply minimum voltage threshold ? card supply undervoltage and overcurrent detection with automatic shutdown ? card pin overvoltage clamp to crdvcc ? card presence detector for acleano and fast shutdown ? consistent card signal sequencing at startup and powerdown, according to iso7816, even on error conditions ? consistent clock signal, even when division ratio or synchronization clock signal are changed aon the flyo during a card session (see figure 29) ? active pulldown on all card pins, including crdvcc , when not in normal operating mode. a current limiting function and an overtemperature detector are limiting power dissipation. esd protection due to the nature of smartcards, the card interface pins must absorb high esd (electro static discharge) energy during card insertion. in addition, the control circuits attached to these pins must safely withstand short circuits and voltage transients during forced card extraction. therefore, the mc33560 features enhanced esd protection, current limitation and short circuit protection on all smartcard interface pins, including c4 and c8 . parallel operation for applications where two or more mc33560 are used, the digital control and data bus lines are common to all mc33560. only the chip select signal, cs , requires a separate line for each interface. while deselected, all communication pins except crdclk will keep their logical state on the card side, and will go to high impedance mode on the microprocessor side. figure 31 shows a typical application of a dual card reader. this arrangement was chosen only to illustrate the parallel operation of two card interfaces in the same module. the discrete capacitor components are necessary to provide low
mc33560 http://onsemi.com 17 impedance on the supply lines vbat and crdvcc and to suppress the high frequency noise due to the dc/dc converter. the load resistors are external in order to adapt the sense current of the acardpresento switches. minimum power consumption considerations all analog blocks except the v bat comparator and the card presence detector are disabled in stand by mode ( cs =h : dc/dc converter stopped). in order to maintain stand by current at a minimum value, all pins with pullup resistance ( cs , int , rdymod ) have to be kept in the high state or left open, and pins with pulldown resistance ( reset , synclk , pwron ) have to be kept in the low state or left open. asyclkin should not be connected to an active clock signal during stand by to avoid dynamic currents. this is valid also for synclk , except that it can be left open. figure 25. example of single sided pcb layout for mc33560 c8 c4 vbat ilim pgnd pwron int c10 r4 c6 c7 rdymod cs reset io invout asyclkin synclk crdgnd crdio crdvcc crdrst crdc8 crddet crdc4 crdclk l1
mc33560 http://onsemi.com 18 figure 26. card signal sequence during v cc power up/down crdvcc rdymod (out) pwron io clk c4. c8 reset crdio crdclk crdc4, crdc8 crdrst cs t won v txh t tr power up power down normal operation seq1 to seq4 seq4 to seq1 figure 27. interrupt servicing and polling t fltout t fltin rdymod (out) cs to int 15 s typ. cs int crddet interrupt servicing interrupt servicing polling polling t drdy
mc33560 http://onsemi.com 19 figure 28. card signal sequence during v cc overload and unexpected card extraction crdvcc rdymod pwron crddet cs t fltin v txh card inserted int v txl t fltout mcu deactivates pwron after card extraction t drdy t dres t dres card extraction mcu polls cs = l, pwron = h crdv cc undervoltage -> rdymod = l overload time smaller than t dres (glitch not to scale) poll with pwron = l -> rdymod = h: card still present rdymod = h poll with pwron = h -> rdymod = l: dc/dc converter overload overload time greater than t dres -> converter stop and crdv cc pull down poll with pwron = l -> rdymod = h: card present 35 ns typ
mc33560 http://onsemi.com 20 figure 29. aontheflyo card clock selection examples rdymod reset io synclk asyclk crdclk cs rdymod reset io synclk asyclk crdclk cs
mc33560 http://onsemi.com 21 figure 30. card reader/writer application c reset q1: xtal 4mhz d1: general purpose diode r1: 47 kohm c1, c2, c4,c5: 10 uf r2: 1 mohm c3: 220 nf l1: murata lqh3c 47 uh r3: 1 mohm c6: 200 nf c7: 10 uf c8, c9: 22 pf m1: 7805 regulator r4: value depending on max. card current z1: general purpose 40 v zener diode u4: card connector connector db9 c2+ gnd c2- vss rx1 tx1 rx2 tx2 rx3 tx3 c1+ vcc c1- vdd do1 di 1 do2 di 2 do3 di 3 mc145407 u3 c5 10 uf c4 10 uf c2 10 uf c1 10 uf 47k r1 d1 reset irq vpp nc pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pb3 nc pb4 pb5 pb6 pb7 vss vdd 0sc1 osc2 tcap pd7 nc tcmp ss c3 sclk mosi miso rdi tdo pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 nc 220 nf c8 22 pf c9 22 pf l1 r3 1m q1 4 mhz r4* u2 mc33560 1 - pgnd 2 - pwron 3 - 4 - rdymod 5 - 6 - reset 7 - io 8 - invout 9 - asyclkin 10 - synclk 11 - crdio 12 - crdgnd int cs ilim - 24 vbat - 23 l1 - 22 c4 - 21 c8 - 20 crdc8 - 19 crdcon - 18 crddet - 17 crdc4 - 16 crdclk - 15 crdrst - 14 crdvcc - 13 c4 clk rst vcc gnd i/o c8 47 uh z1 c10 0.1 uf m1 7805 8..40 vdc card detect u4 c7 10 uf c6 200 nf card slot r2 1m mc68hc705c9 u1 + + +
mc33560 http://onsemi.com 22 figure 31. multi slot card reader/writer application c reset vbat reset irq vpp nc pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pb3 nc pb4 pb5 pb6 pb7 vss vdd 0sc1 osc2 tcap pd7 nc tcmp ss sclk mosi miso rdi tdo pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 nc mc33560 1 - pgnd 2 - pwron 3 - 4 - rdymod 5 - 6 - reset 7 - io 8 - invout 9 - asyclkin 10 - synclk 11 - crdio 12 - crdgnd int cs ilim - 24 vbat - 23 l1 - 22 c4 - 21 c8 - 20 crdc8 - 19 crdcon - 18 crddet - 17 crdc4 - 16 crdclk - 15 crdrst - 14 crdvcc - 13 c4 clk rst vcc gnd i/o c8 card detect mc68hc705 mc33560 1 - pgnd 2 - pwron 3 - 4 - rdymod 5 - 6 - reset 7 - io 8 - invout 9 - asyclkin 10 - synclk 11 - crdio 12 - crdgnd int cs ilim - 24 vbat - 23 l1 - 22 c4 - 21 c8 - 20 crdc8 - 19 crdcon - 18 crddet - 17 crdc4 - 16 crdclk - 15 crdrst - 14 crdvcc - 13 c4 clk rst vcc gnd i/o c8 card detect vbat vbat
mc33560 http://onsemi.com 23 marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week so24w dw suffix case 751e tssop24 dtb suffix case 948k 1 24 mc33560dw awlyyww 1 24 mc335 60 alyw
mc33560 http://onsemi.com 24 package dimensions (tssop24) dtb suffix plastic package case 948k01 issue o dim min max min max inches millimeters a 7.70 7.90 0.303 0.311 b 5.50 5.70 0.216 0.224 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 7.60 bsc 0.299 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ??? ??? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 13 24 12 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 24x ref k n n
mc33560 http://onsemi.com 25 package dimensions (so24l) dw suffix plastic package case 751e04 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t t g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029
mc33560 http://onsemi.com 26 notes
mc33560 http://onsemi.com 27 notes
mc33560 http://onsemi.com 28 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33560/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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